“Because of its deep understanding of clock signals, Dapu has inherent advantages in buffer design, which can perfectly match the clock source and buffer characteristics to output ultra-low jitter clock signals. Dapu has launched a variety of single-ended and differential output buffers. Currently, there are more chips on the way of research and development and will be launched soon. Multiple series of high-stability clock and buffer products, as well as other clock chips, can provide customers with “one-stop” “Formula”, the best matching solution.
Generally speaking, the fan-out clock buffer (Buffer), the main functions can be divided into clock signal replication, clock signal format conversion, clock signal level conversion. Below we introduce several typical application scenarios for these functions.
Typical Application 1: Clock Signal Replication
The simple understanding of clock signal replication is to generate multiple clock signals by frequency replication of one clock source signal.
Figure 1, the functional block diagram of INS6104A, it can be seen from the figure that 1 channel of clock signal input is divided into 4 channels of the same clock signal output, and the signal output can be controlled through the OE pin.
Figure 1: INS6104A functional block diagram
For example, on a certain PC control motherboard, there are multiple chips such as CPU, CPLD, network processing ASIC, clock generator, etc., which all require a 25MHz reference clock signal. The options you can choose are:
Option 1: Choose a crystal oscillator to provide reference for several chips at the same time. The big drawback of this solution is the clock signal integrity problem. This kind of point-to-multipoint connection cannot achieve impedance matching, and the signal reflection will be very serious, resulting in the monotonicity of the clock signal edge, overshoot ringing and other problems, which may lead to false triggering and cause the system to lose synchronization. Therefore, most applications use A point-to-point topology is required.
Figure 2: Single crystal solution
Option 2: Select 4 crystal oscillators to provide reference for the 4 chips respectively. The advantage of this solution is that the PCB layout is more flexible and convenient, which can ensure the integrity of the clock signal. Of course, the obvious disadvantage is the high cost, especially for scenarios with high reference frequency index requirements, the high-performance crystal oscillator itself has a high cost, and the power consumption is often relatively high. The processing of the power supply will further increase the cost of the solution. In addition, while the layout is flexible, it will also take up more PCB board space.
Figure 3: Multiple Crystal Solutions
Option 3: A crystal oscillator plus a clock buffer (Buffer) chip, which is also the most commonly used solution. Through the frequency replication function of Buffer, a point-to-point topology can be achieved, which can solve the problem of signal integrity and achieve the best cost performance.
Figure 4: Crystal and Buffer Solutions
Typical Application 2: Clock Signal Format Conversion
In addition to clock signal replication, there are many clock buffers that also have the function of format conversion of clock signals, which is to convert an input clock signal of one format into an output of another format.
The following figure is the functional block diagram of two Buffers with this function. The input can be selected from any of the 3 channels. The signal formats supported by input ports 0 and 1 can be any of LVPECL, LVDS, HCSL, SSTL, LVCMOS, and LVTTL. One, while the OSC input port supports passive crystal input. The INS6110 can convert any type of input clock signal into 10 channels of LVCMOS single-ended output clock signals, while the INS6310 can output a total of 10 channels of differential clocks and 1 channel of LVCMOS single-ended clocks from 2 banks. The differential output clock type can be configured separately through OTYPEA[1:0]and OTYPB[1:0]and select LVPECL, LVDS, HCSL or high-impedance state.
INS6110 functional block diagram
Figure 5: Single-ended output buffer functional block diagram INS6310 functional block diagram
INS6310 functional block diagram
Figure 6: Functional Block Diagram of Differential Output Buffer
In data center, server, network monitoring equipment and other applications, many chips communicate through PCIe interface, such as CPU, PCIe switch chip, PCIe expansion card, Wifi controller, GE port, etc., all use PCIe port to transmit high-speed Data, the system needs multiple 100M reference clocks in HCSL format, and there is no crystal oscillator that directly outputs HCSL signals in the market. At this time, the crystal oscillator output by 100M LVDS or LVPECL can be converted into 100M HCSL clock signal format through Buffer to meet the application. .
Figure 7: Clock Signal Format Conversion
Typical Application 3: Clock Signal Level Conversion
In Figure 5 and Figure 6, you may have noticed that they all have VDD, VDDOA, VDDOB and other power sources. Here VDD is the core voltage and the voltage of the input clock signal, while VDDOX is the output signal voltage, VDDOX voltage It can be different from VDD. For example, VDD is 3.3V, and VDD can choose 3.3V, 2.5V, 1.8V and other voltage output. This is the third typical application of clock buffer, that is, the level conversion of clock signal. When the reference frequency level required by the existing frequency source and the actual chip is different, the level conversion of the clock signal can be realized through the clock buffer.
The above cases can be seen: the clock buffer (Buffer) is inseparable from the crystal or crystal oscillator. A separate clock buffer cannot generate a frequency source by itself. It can copy, format and level shift the clock signal generated by a crystal or crystal oscillator. In application scenarios that require these functions, selecting an appropriate clock buffer can greatly optimize the system clock scheme and cost performance.
Dapu Communication has been deeply involved in the field of time and frequency for nearly 20 years, focusing on the research and development of high-stability clocks. Its current products include Timing Server, Clock Module, OCXO, TCXO, SPXO, Crystal and other series, which conform to the international clock level standard GR-1244-Core 1 ~Level 4, the performance index is at the leading level in the industry.
Because of its deep understanding of clock signals, Dapu has inherent advantages in buffer design, which can perfectly match the clock source and buffer characteristics to output ultra-low jitter clock signals. Dapu has launched a variety of single-ended and differential output buffers. Currently, there are more chips on the way of research and development and will be launched soon. Multiple series of high-stability clock and buffer products, as well as other clock chips, can provide customers with “one-stop” “Formula”, the best matching solution.